AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM9
Patterning Options for 14nm Node and Beyond

Tuesday, October 30, 2012, 10:40 am, Room 25

Session: Advanced FEOL/Gate Etching 2
Presenter: Y. Yin, IBM Res. at Albany Nanotech
Authors: Y. Yin, IBM Res. at Albany Nanotech
R. Jung, IBM Res. at Albany Nanotech
F. Lie, IBM Res. at Albany Nanotech
M. Beard, IBM Res. at Albany Nanotech
B.G. Morris, IBM Res. at Albany Nanotech
M. Hartig, IBM Res. at Albany Nanotech
S. Kanakasabapathy, IBM Res. at Albany Nanotech
Y. Mignot, STMicroelectronics
Y. Xu, IBM Res. at Albany Nanotech
C. Koay, IBM Res. at Albany Nanotech
L. Jang, GLOBALFOUNDRIES
N. Saulnier, IBM Res. at Albany Nanotech
J. Abdallah, IBM Res. at Albany Nanotech
H. Chen, IBM Res. at Albany Nanotech
M. Tagami, Renesas Electonics
K. Akarvardar, GLOBALFOUNDRIES
S. Akarvardar, GLOBALFOUNDRIES
J. Arnold, IBM Res. at Albany Nanotech
T. Spooner, IBM Res. at Albany Nanotech
M. Colburn, IBM Res. at Albany Nanotech
Correspondent: Click to Email
Beyond the 22nm node, limitations of traditional patterning processes become critical. Conventional 193nm immersion lithography is not able to resolve features below 40nm half pitch with a single exposure for Front, Middle and Back Ends of Line. Patterning vias at appropriate CD and spacing is equally challenging. Until further wavelength scaling through Extreme Ultraviolet (EUV) the industry’s attention is focused on Double Patterning. Pitch Splitting (PS) Lithography and Sidewall Image Transfer (SIT) are the two broad categories of techniques that have been under evaluation for sub-22nm nodes. Moreover, as we keep shrink the key features to dimensions of interest to sub-14nm nodes, innovations on existing double patterning techniques and the introduction of emerging patterning techniques such as directed self-assembly are needed in order to enable sub-40nm pitch features patterning. In this talk we will address the innovations further needed on existing double patterning methods and discuss the opportunities and challenges of emerging advanced patterning techniques in order to meet the patterning requirements for 14nm node and beyond.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.