AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM6
Key Challenges in FinFET FEOL RIE Processing at the 14nm CMOS Node and Beyond

Tuesday, October 30, 2012, 9:40 am, Room 25

Session: Advanced FEOL/Gate Etching 2
Presenter: R.M. Martin, IBM Corporation
Authors: R.M. Martin, IBM Corporation
A. Banik, IBM Corporation
J. Chang, IBM Corporation
R. Jung, IBM Corporation
S. Kanakasabapathy, IBM Corporation
M. Kobayashi, IBM Corporation
Q. Lin, IBM Corporation
B.G. Morris, IBM Corporation
S.C. Seo, IBM Corporation
T. Standaert, IBM Corporation
K. Stein, IBM Corporation
R. Sreenivasan, IBM Corporation
H. Wang, IBM Corporation
M. Yang, IBM Corporation
Q. Yang, IBM Corporation
Y. Yin, IBM Corporation
D.H. Choi, GLOBALFOUNDRIES
R. Kambhampati, GLOBALFOUNDRIES
T. Kwon, GLOBALFOUNDRIES
Correspondent: Click to Email
For CMOS nodes at 22nm and below, the gate critical dimensions become small enough so that conventional methods for addressing issues such as short channel effects on planar devices become ineffective. Fortunately, alternative non-planar devices are becoming mature enough so that they can be used at these next generation technology nodes. Development of new processes to build such three dimensional structures present new challenges for both lithography and plasma etching. In this presentation, we will review processes for building finFET devices in the front end of line (FEOL) from a patterning perspective. Below 80nm print pitch, double patterning methods such as sidewall image transfer (SIT) and pitch split can be employed, however, these more complex methods require additional precision in the plasma etching profile and selectivity to avoid issues such as pitch walking and line edge roughness. Furthermore, at these smaller dimensions and with the complication of 3 dimensions, issues such as RIE lag become much more apparent. Challenges such as these, and some of their potential solutions will be discussed.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.