AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM5
Spacer Patterning for Trigate SOI Devices

Tuesday, October 30, 2012, 9:20 am, Room 25

Session: Advanced FEOL/Gate Etching 2
Presenter: S. Barnola, CEA, LETI, MINATEC Campus, France
Authors: S. Barnola, CEA, LETI, MINATEC Campus, France
P. Pimenta-Barros, CEA, LETI, MINATEC Campus, France
L. Desvoivres, CEA, LETI, MINATEC Campus, France
J. Pradelles, CEA, LETI, MINATEC Campus, France
S. Barraud, CEA, LETI, MINATEC Campus, France
Correspondent: Click to Email
Demonstrations of Trigate SOI devices recently reported highlight a better scalability with improved subthreshold slope and immunity to short channel effect for aggressively scaled CMOS Si devices. However, there are several key challenges in these devices to achieve high performance. Extremely narrow and uniform silicon fins are required combined with increased fin pitch in order to improve the effective channel width and then, the drive current. This work aims to demonstrate Si fin pattern with a width of 10nm and a fin pitch of 35nm.It is no possible to create 10nm dense active features by using only 193nm immersion lithography because of its optical limitations. Consequently, several approaches have been developed in order to reach ITRS predictions, such as e-beam lithography, Extreme UV, negative tone development, block copolymer, and Self-Aligned Double Patterning (SADP). Regarding the technical issues that remain to be solved for each approach, SADP is one of the most promising solutions for the 14nm technology node and below.SADP approach includes at least 3 steps (lithography, spacer deposition, spacer and Si etching) to divide by 2 the pitch of the 1st lithography. For practical reasons and for reducing the number of SADP steps, e-beam lithography has been used to create the “mandrel” patterns that support the spacers. The e-beam initial pitch is 70nm, whose CD has to be reduced to 25nm by a trimming step to reach the final 35nm pitch after SADP. The integration scheme investigated in this work includes the following steps: e-beam lithography with trilayer stack, resist trimming, trilayer etching, SiARC removal, spacer deposition, spacer etching and SOC stripping. All plasma etching steps were carried out on 300mm ICP LAM VERSYS.One of the major challenges of this SADP integration was to limit the Si and SiO2 consumption from the SOI substrate during the SADP process steps. We also had to consider the impact of the non-symmetrical spacers on the micro-loading effect during Si etching. Integration scheme with a buffer layer has been investigated to limit the Si and BOX consumption, but this approach makes CD control more complicated. Thus, we have compared the two integration schemes, with and without buffer layer, in term of CD control and profile to achieve the requirements for this FEOL application for SOI technology.