AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Invited Paper PS2-TuM3
Plasma Prize Talk: Grand Challenges in Etch

Tuesday, October 30, 2012, 8:40 am, Room 25

Session: Advanced FEOL/Gate Etching 2
Presenter: S. Sriraman, Lam Research
Authors: R. Gottscho, Lam Research
S. Sriraman, Lam Research
Correspondent: Click to Email
Plasma etching has enabled the perpetuation of Moore’s Law from >1 um to now less than 20 nm. More than ever, plasma etching is used to enable the extension of semiconductor device fabrication into the nanoelectronics age. The industry has always faced etch challenges due to scaling laws, especially as we begin to manufacture features that require atomic etch precision. Etch precision is especially challenging as the industry moves to 3D architectures, as we are etching electrically active layers in structurally complex features. Also, though we’ve always had to etch high aspect ratios, the fundamental challenge of aspect ratio dependent etching is now through alternating thin materials. The additional challenge to control wafer edge effects and reduce cost of consumables is ever more critical with compounding effects of multiple passes needed to compensate for lithographic limitations. In this presentation, I will give an overview of where we currently stand on our understanding of the origins and some solution approaches to the grand challenges in etch.