AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM2
Tracking Line Width Roughness Improvement during Gate Plasma Patterning

Tuesday, October 30, 2012, 8:20 am, Room 25

Session: Advanced FEOL/Gate Etching 2
Presenter: L. Vallier, CNRS, France
Authors: L. Vallier, CNRS, France
E. Pargon, CNRS, France
N. Posseme, CEA, LETI, MINATEC Campus, France
L. Azarnouche, CNRS, France
S.D. Nemani, Applied Materials Inc.
C. Rosslee, Applied Materials Inc.
T. Pham, Applied Materials Inc.
Correspondent: Click to Email
The effect of line width roughness (LWR) on the performance characteristics of transistor gates becomes problematic as the critical dimension (CD) of the gate decreases. Minimizing the magnitude of LWR in patterned features is becoming mandatory for the next technological nodes and is actually requested by the International Technology Roadmap for Semiconductor. Showing up particularly at 193nm wavelength exposure, the photoresist (PR) LWR is the main contributor to the final LWR measured in silicon gates following plasma patterning; therefore most of the effort is focused on the PR LWR reduction prior to the plasma transfer. At the same time, it was observed that the magnitude of LWR decreased when transferred from resist into the gate material. Plasma action might further help in the LWR reduction. In this work we have implemented the Power Spectrum Density (PSD) method as a measure of the LWR spatial frequencies distribution of a line, to monitor its evolution during the patterning of silicon gates with plasma etching process, starting from the PR after lithography up to the Silicon gate line. Thanks to the PSD method, noise coming up from CD SEM pictures of PR lines acquired at very low electron fluency can be subtracted, enabling a real LWR measure of the line with associated frequencies. A robust protocol for the CD SEM data treatment was developed and applied to various process conditions, aiming to obtain the best LWR reduction. Several cure treatment of the PR, achieved prior to the plasma etching of the gate, were investigated with the combination of UV light, plasma exposure using different gas chemistries, thermal treatment, pulsed plasma and E-beam exposure. This work confirms that the etch process can reduce the magnitude of roughness in silicon over a range of mid and high spatial frequencies, that is smoothing the line, however the extent of this roughness reduction vanishes as the resist LWR reaches its minimum. These results demonstrate that plasma action during the gate etch cannot improve the LWR much and post-etch LWR in silicon may be limited by the minimum LWR achievable in resist, therefore pushing for efficient PR cure treatment where plasma exposure play a key role. Based on the PR material used in this study which presents a 6.5 nm initial LWR value after lithography, a LWR of 2.9 nm was measured after the best LWR reduction process highlighting the need for further improvement to match the LWR requirement of the next technological nodes.