Moore’s law dictates continuation of shrinkage of transistors to make smaller, faster and less power-consuming devices at lower cost. FinFET (3-D) devices are needed to continue Moore’s law. Anisotropy and selectivity requirements in FEOL etches (e.g., FinFET gate) are becoming very demanding and conventional RF plasma sources are hitting their limits to achieve such requirements. Microwave power delivered through radial line slot antenna generates over-dense evanescent microwave plasma just below top dielectric plate, and the electrons cools down (1eV or less in wafer region) due to inelastic collisions with the background gas. Low electron temperature (Te), low self-bias (Vdc) and low plasma potential in evanescent microwave plasmas enable “soft” etching for the 22nm generation and beyond technology nodes. In this study, Si-gate etching was performed in a evanescent microwave plasma system to achieve high selectivity over silicon oxide and silicon nitride with vertical profile. In addition to low self-bias, low Te is required to obtain high Si selectivity over SiO2 due to low-dissociation of by-products in evanescent microwave plasmas. Re-dissociated by-products (e.g., SiBrx*) pull out O- from SiO2 resulting in loss of Si selectivity over SiO2. Low Te (low re-dissociation) also helps with control of iso-nested CD-loading. High ion-flux with low Te plasma yields vertical profile of Si independent of aspect ratio and with minimal iso-nested CD-loading. Various other interesting aspects will also be presented.

 

This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY 12222. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.