Over the last couple of technology nodes (from 45 nm node and beyond), Trench First Metal Hard Mask (TFMHM) integration scheme has gained traction and become the preferred integration of low-k materials for BEOL. This integration scheme also enables Self-Aligned Via (SAV) patterning which prevent via CD growth and confines via by line trenches to better control via to line spacing. Also for the 64 nm pitch technology and below, TFMHM is well suited for double patterning of the line definition required for the ever smaller line pitches of the most critical BEOL levels. In the SAV process, temperature, gas chemistry, power and pressure were shown to be key process parameters to meet the metal HM selectivity requirements. The flexible adjustment of the ion energy and control of the flux of ions and active neutrals was shown to be critical to meet the metal HM selectivity requirements for both SAV and trench etching. The TFMHM integration at these dimensions requires careful and controlled metal HM selectivity. These tight technology requirements at these ever smaller pitches also challenge hardware to bring evolutionary improvements to enable wider process windows to meet tighter process specifications. In this paper, the RIE efforts on process controls of the via and trench profiles, the metal HM selectivity management and hardware solutions to address the dielectric RIE challenges associated to TFMHM scheme at 64 nm pitch and below will be discussed.

This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY 12203.

This work has also been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533.