As the dimensions of microelectronic circuits scale down, the gate linewidth roughness (LWR) increasingly impacts the electrical performances of transistors. It has previously been shown that the significant photoresist (PR) sidewall roughness after lithography is transferred into the gate during the subsequent plasma etching process, resulting in a final gate LWR far above the ITRS requirements. The key to reduce the gate LWR is to minimize the photoresist LWR before plasma transfer. Plasma treatments are commonly used for that purpose. In previous studies, we have shown that photoetching mechanisms occurring during plasma exposure plays a key role in PR smoothening. We have also demonstrated that the carbon species outgassed during the treatment can redeposit on the PR pattern sidewalls and degrade the LWR. Moreover, we have shown the benefit of applying a bake after plasma treatment in order to further decrease the LWR. From this knowledge, we develop a new treatment based on HBr/O₂ plasma exposure followed by a bake. The plasma conditions are optimized in order to emit strongly in the vacuum ultra violet (VUV) range (below 200 nm) and to prevent carbon redeposition on the resist sidewalls. We show that by controlling the VUV dose (mainly by tuning source power or plasma exposure time), the PR bulk can be either softened (photolysis) or strengthened (crosslinking). Moreover, the formation of the carbon deposit on the resist surface can be controlled by the O₂ content of the plasma. The surface and bulk properties of the PR line after plasma treatment will determine the LWR behavior during the subsequent thermal cure treatment. A soft resist bulk combined with a thin surface carbon layer is the ideal case to get the best LWR smoothening during the bake without reflowing. By optimizing both the plasma oxygen content and VUV dose, we obtain a 60% LWR decrease after bake reducing the LWR from 7.3 nm to 2.9 nm.