AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Thursday Sessions
       Session PS-ThP

Paper PS-ThP28
The Effect of a Low Plasma-Induced Damage Etching on sub-32nm Metal Gate/High-k Dielectric CMOSFETs Characteristics

Thursday, November 1, 2012, 6:00 pm, Room Central Hall

Session: Plasma Science and Technology Poster Session
Presenter: K.S. Min, Sungkyunkwan University, Republic of Korea
Authors: K.S. Min, Sungkyunkwan University, Republic of Korea
S.H. Kang, Sungkyunkwan University, Republic of Korea
G.Y. Yeom, Sungkyunkwan University, Republic of Korea
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According to international technology roadmap for semiconductors (ITRS), as the critical dimension (CD) of metal-oxide-semiconductor field effect transistor (MOSFET) is scaled down to 45nm node and below, the present gate (poly-Si) with a high-k dielectric is intrinsically limited. Therefore, a metal gate compatible with a high-k dielectric, which is physically thicker with the same equivalent oxide thickness (EOT) has been investigated. For the etching of metal gate/high-k dielectric, reactive ion etching technique is currently applied to maintain accurate CD by etching the gate structure anisotropically with minimal damage on substrate. However, it can introduce plasma induced damages (PIDs) and was found to degrade the electric characteristics of metal gate/high-k dielectric CMOSFETs, particularly in the short channel devices. For low standby power (LSTP) application, an etch technique with low plasma-induced damage composed of neutral beam etching and atomic layer etching has been applied to metal gate and high-k dielectric etching of complementary metal-oxide- semiconductor field effect transistors (CMOSFETs), respectively, and their electrical characteristics were compared with those etched by conventional wet and dry etching techniques. It has been found that, after the etching using the low plasma-induced damaged etching technique, device performances have been improved compared to those etched by conventional wet and dry etching techniques. Especially, gate induced drain leakage and Ioff which are key factors for LSTP have been reduced significantly.