AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Thursday Sessions
       Session PS-ThP

Paper PS-ThP1
Plasma Etch Challenges to Produce Metallization-Friendly Profiles at 20nm and Beyond Technology Nodes in the BEOL

Thursday, November 1, 2012, 6:00 pm, Room Central Hall

Session: Plasma Science and Technology Poster Session
Presenter: Y. Mignot, STMicroelectronics
Authors: Y. Mignot, STMicroelectronics
R. Koshy, GLOBALFOUNDRIES
Y. Park, Samsung Electronics Co. Ltd.
R. Srivastava, GLOBALFOUNDRIES
E. Soda, Renesas Electronics
Y. Yin, IBM Microelectronics
M. Beard, IBM Microelectronics
B.G. Morris, IBM Microelectronics
K. Trevino, GLOBALFOUNDRIES
J. Arnold, IBM Microelectronics
S. Allen, IBM Microelectronics
C. Labelle, GLOBALFOUNDRIES
M. Sankarapandian, IBM Microelectronics
Y. Loquet, STMicroelectronics
Y. Feurprier, Tokyo Electron Technology Center, America, LLC
L. Wang, Tokyo Electron Technology Center, America, LLC
J. Stillahn, Tokyo Electron Technology Center, America, LLC
Y. Chiba, Tokyo Electron Technology Center, America, LLC
V. Gizzo, Tokyo Electron Technology Center, America, LLC
K. Kumar, Tokyo Electron Technology Center, America, LLC
C.A. Wang, GLOBALFOUNDRIES
Q. Zhang, GLOBALFOUNDRIES
A. Inada, Renesas Electronics
S. Mignot, STMicroelectronics
Correspondent: Click to Email
As feature critical dimension (CD) shrinks towards and beyond the 14nm node, new patterning techniques within the context of a trench-first-metal-hard-mask (TFMHM) patterning scheme have been developed to generate trenches and vias below 100nm pitch. One of the main challenges at advanced nodes is to create structures (i.e., trenches & vias) that can be robustly metalized This requires several elements of focus for the etches: first, there must be zero dielectric etch damage that results in undercut of any hard masks in the film stack; second, the aspect ratio of the final etch structure must be minimized; and third, the shape of the trench or via profile must be tailored to be metallization-friendly (i.e., slight angle better than vertical). These requirements often conflict with each other, especially within a patterning scheme that requires self-aligned vias, where the desired high selectivity to the hard mask conflicts with the need to minimize the amount of hard mask left in order to decrease aspect ratio. In this paper, we will discuss some of the approaches that we have investigated to achieve the best profile for metallization. This includes plasma etch all-in-one (AIO) dielectric etch optimization as well as multi-step solutions that potentially can use techniques including wet chemistries, ion beam metal etching, and dry metal etching. In addition, data will be presented on efforts to minimize overall metal-related residues observed as a function of the pattern density and thus, metal exposure. Metal-containing etch byproducts have also been observed and the material characteristics and/or morphology of these etch byproducts can vary across the wafer, producing non-uniform residue patterns and affecting the plasma etch erosion of the metal hard mask itself. Understanding the underlying mechanisms of observed metal-induced defects (i.e., residues, etch byproducts, etc.) is key to applying the correct plasma etch optimization to eliminate or minimize the effects. Some data will be presented showing the progress that has been made on these issues.