Paper PS-MoM5
High Selective Etching of SiN Based Material Over Si and SiO₂ using Evanescent Microwave Plasma for FINFET Spacer Applications

Monday, October 29, 2012, 9:40 am, Room 25

For smaller than 22nm technology node devices, a FinFET (3-D) gate structure is needed to reduce gate leakage, decrease power consumption, increase drive current and control short channel effects. FinFET gate spacer etching presents challenges for conventional RIE process, since it requires highly anisotropic and selective etching of Silicon Nitride over Si/SiO2. Microwave power was delivered through radial line slot antenna generating high density evanescent microwave plasma. High density evanescent microwave plasmawith low self-bias at the wafer enables a highly selective and anisotropic etching of spacer. The bulk electron energy distribution determines the gas phase reaction rates that generate various radicals and ionic species. The etchant, passivant and ion flux to the wafer can be controlled by the energy distribution of Bulk electrons (T_e). T_e can be tuned in by adjusting the microwave power. High SiN selectivity over Si and SiO2 was achieved on blanket as well as patterned wafer using the evanescent microwave plasma etcher. In general, selectivity is achieved by controlling the polymer layer difference over SiN/Si/SiO2. The difference of pattern wafer/blanket wafer etch rates/selectivities can be explained by differences in transport of by ions and radicals through high aspect ratio features. The effects of loading of SiN, Si and resist materials on etch rates and selectivity will be reviewed.

This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY 12222. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities