The spacer etch process is a very critical element in the CMOS device process flow as it ensures and enables the electrical isolation of Source/Drain and Gate regions. We observed that during conventional spacer processes, very little difference in plasma polymer deposition onto the respective substrates could be noted. [1] A successful Nitride Spacer process was rather facilitated by a silicon etch process that was selective to oxide, where excess oxidation lead to a conversion of Silicon to Silicon oxide. This also means that the etch rates of the Nitride are limited by the simultaneous oxidation of the nitride. A potential solution to overcome this limitation would be to control the etch rate by polymer thickness, similar to high selectivity oxide etching. An evaluation of this approach has yielded similar results as the general etch mechanism proposed by Standaert et al. [2] A novel etch chemistry was also evaluated that enables a different etch mechanism that cannot be described by the general model.

The impact of this novel mechanism on spacer etch processes was evaluated for both, capacitive and inductive discharges. We furthermore evaluated the impact of this novel process on planar and non-planar device structures. The novel gas chemistry has also been evaluated to enable an oxygen free spacer process. We found that the lateral spacer loss can be eliminated and that Si loss can be effectively reduced by employing the novel process. The SiN footing can be effectively reduced by fine-tuning the ion/neutral ratio of the plasma discharge. The best results to date from a PDSOI 22nm testsite have yielded an SOI loss of about 2nm which is able to maintain all SiN on the gate sidewall while keeping the HM loss to about 4nm and reducing the SiN foot to less than 3nm.

 

[1] S. Engelmann et al., AVS 58th Int. Symp. & Exhibit. (2011)

[2] M. Schaepkens et al., J. Vac. Sci. Technol. A 17, 26 (1999)