AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM10
Detailed Analysis of Si Substrate Damage Induced by HBr/O2- and H2-Plasma Etching and the Recovery Process Designs

Monday, October 29, 2012, 11:20 am, Room 25

Session: Advanced FEOL/Gate Etching 1
Presenter: K. Eriguchi, Kyoto University, Japan
Authors: Y. Nakakubo, Kyoto University, Japan
A. Matsuda, Kyoto University, Japan
M. Fukasawa, Sony Corporation, Japan
Y. Takao, Kyoto University, Japan
T. Tatsumi, Sony Corporation, Japan
K. Eriguchi, Kyoto University, Japan
K. Ono, Kyoto University, Japan
Correspondent: Click to Email
Hydrogen-containing plasmas have been widely used for fabricating Si-based electronic devices such as metal–oxide–semiconductor field-effect transistor (MOSFET). Plasma-induced Si substrate damage during shallow trench isolation and gate electrode formation processes has become one of the critical issues because the damaged structure is believed to not only degrade the electric performance but also enhance the parameter variations resulting in yield loss in mass production [1]. Due to its light mass, a hydrogen atom from plasma can penetrate deeper in Si substrate, and, consequently, forms the thicker damaged layer leading to the larger amount of Si loss in the source /drain extension region of MOSFET called “Si recess” [2]. Although the recovery mechanism of Si damage has been extensively studied, there have been few comprehensive process-design guidelines by taking into account the electrical characteristic degradation. In this study, we report detailed analyses of Si-damage recovery dynamics using a capacitance–voltage (C–V) technique, and provide respective recovery process guidelines for HBr/O2- and H2-plasma cases. Silicon wafers with thermal-oxide layer (2 nm) were damaged by HBr/O2-and H2-plasma treatments. Various annealing processes in N2 ambient with different “thermal budgets” were employed to address the impacts of the temperature and budget on the damage recovery. An SiO2-Capping layer was formed on some samples to simulate structural constraints in present-day MOSFET processes. Using the quantitative C–V technique (1/C2-based analysis), we found that, although HBr/O2-plasma induced a larger amount of Si damage (defect site), wet-etch stripping process was more effective due to thinner damaged layer thickness, further, the annealing process with temperatures higher than 850 ºC was found to be able to cure the structural defects. As for H2-plasma cases, on the other, the wet-etch was “insufficient” to remove the defects, resulting in a high conductive layer. Moreover, we observed that the annealing temperature (> 1050 ºC) rather than the budget was a primal parameter to cure the damage. The obtained results may be explained by “the defect-density or structural-constraint effect”. The present findings imply an important and useful guideline of the recovery process design of H-containing-plasma damage in future advanced devices. [1] K. Eriguchi et al.: J. Vac. Sci. Technol. A 29, 041303 (2011).[2] M. Fukasawa et al.: J. Vac. Sci. Technol. A 29, 041301 (2011).