AVS 59th Annual International Symposium and Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM1
Selective Etching of Spacer with Pulsing in Inductively Coupled Plasmas for FinFET Devices

Monday, October 29, 2012, 8:20 am, Room 25

Session: Advanced FEOL/Gate Etching 1
Presenter: G. Upadhyaya, Lam Research Corp
Authors: B. Zhou, Lam Research Corp
M. Titus, Lam Research Corp
P. Friddle, Lam Research Corp
M. Robson, Lam Research Corp
G. Upadhyaya, Lam Research Corp
G. Kamarthy, Lam Research Corp
S. Kanakasabapathy, IBM Corp
E. Franke, IBM Corp
Correspondent: Click to Email
The transition to 14 nm technology node has introduced an architectural shift from traditional planar devices to complex three-dimensional FinFET structures. A primary etch challenge for making FinFET devices is that of spacer etch wherein the topography of the FinFET devices requires the fin surface (Si) to withstand substantial over-etch in order to remove the spacer on the fin sidewalls. Typical targets for this etch comprises of < 1nm Si recess, good spacer profile fidelity, complete spacer removal on fin sidewalls and < 2nm spacer CD loss. With conventional etch methodologies, the process window for achieving these targets is narrow due to competing deposition and etch species that simultaneously co-exist in the plasma. Simply lowering the electron temperature or lowering the ion energy is not a solution since there is a tradeoff between spacer CD loss and Si recess. In this presentation, we will demonstrate that by using pulsing, the deposition and etch phases can be separated thereby yielding a wide process window and breaking the tradeoff to enable FinFET spacer etch. Various pulsing schemes will be contrasted with conventional continuous mode operation along with a discussion of the compatibility of the pulsed spacer process with downstream integration.