AVS 58th Annual International Symposium and Exhibition | |
Plasma Science and Technology Division | Tuesday Sessions |
Session PS-TuM |
Session: | Advanced BEOL / Interconnect Etching I |
Presenter: | Christopher Cole, TEL Technology Center, America, LLC |
Authors: | C. Cole, TEL Technology Center, America, LLC A. Ko, TEL Technology Center, America, LLC A. Ranjan, TEL Technology Center, America, LLC T. Enomoto, TEL Technology Center, America, LLC A. Metz, TEL Technology Center, America, LLC K. Kumar, TEL Technology Center, America, LLC P. Biolsi, TEL Technology Center, America, LLC E. Wornyo, IBM Research H. Yusuff, IBM Research S. Allen, IBM Research R. Wise, IBM Research C. Labelle, GlobalFoundries T. Chen, GlobalFoundries S. Kanakasabapathy, IBM Research Y. Mignot, STMicroelectronics |
Correspondent: | Click to Email |
As device dimensions continue to shrink, uniformity of etch rate/feature depth and critical dimension becomes very important. Capacitively coupled plasma (CCP) sources have advantage in terms of uniformity over non-planar sources in addition to design simplicity, reliability and wide process window. Wide-gap CCPs have been used for front-end etch applications where as small-gap CCPs are work-horse for back-end dielectric etch. Recently, studies on mid-gap CCPs indicates that inter-electrode spacing of ~100mm is best suited for etch rate and CD uniformity. In our studies, for tri-layer mask etch and TiN hard-mask etch, mid-gap CCP achieved uniformity of <1nm (3σ) CD and ~1% (3σ) etch rate. Mid-gap CCPs have 20-30% higher etch rate compared to wide-gap CCPs. Power on top electrode can be divided to center and edge for control of plasma density distribution. Design changes in pumping port assembly effectively create uniform confined plasma without plasma leaking through pump-port. Plasma confinement helps in creating denser plasma at relatively lower RF power. Using above-mentioned “knobs”, flat etch rates and CDs were achieved in mid-gap CCPs.
This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY 12222. This work has also been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533.