Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the 22-nm node device manufacturing. However, a major issue is the necessity to use thin photoresist (between 55-nm and 80-nm after development) because of resolution requirement and limited depth of focus. In addition, its low etch resistance does not allow high aspect ratio pattern transfer. In this context, a new hardmask strategy called spin-on trilayer resist system has been considered.

In this work, we mainly focus on the etch patterning capability of narrow pitch dual damascene structures by using EUVL combined with a spin-on trilayer resist system. The latter consists of three layers. The photoresist on top is used to pattern a thin spin-on glass layer which is then used to pattern a thick spin-on carbon layer (SOC). The SOC has two functions. It is used for its good gap-filling capability to avoid patterning over nonplanar surfaces but it also acts as a hardmask to pattern the dielectric stack (150-nm of oxide on top of 15-nm of SiCO and 5-nm of SiCN). Regarding the dual damascene architecture, two different approaches have been considered: the via-first and the trench-first. Despite few challenges such as the well-known fencing issue, the via-first approach has been chosen as it is less sensitive to misalignment. In this scheme, two lithography and etch steps are needed, first to form the via then to pattern the trench and etch the barrier layer. In this study, we compared the via opening by using the standard PECVD carbon layer and by using the SOC layer. As expected, the PECVD carbon layer has a better process window compared to the SOC layer. The selectivity is greater and allows many chemistry variations to fine tune for instance the profile. To get similar process window with the trilayer resist system, we introduced C4F8 and CO to substitute C4F6 and O2 in the original chemistry. This modification clearly improved the process by having a better control on the passivation layer formation. Regarding the trench opening, we observed a significant line wiggling of the SOC hardmask for 50-nm half-pitch structures and beyond. We characterized this instability thanks to stress measurements and we kept it under control by changing three different process parameters: the bottom electrode temperature, the baking conditions after coating and the film thickness. Each of them has an impact but the best result came from combining all three together.

 

To conclude, we demonstrated that narrow pitch dual damascene structures can be obtained by using EUVL in association with a spin-on trilayer resist system. The structures formed in this way shows good electrical characteristics.