One major challenge in plasma etching processes for sub-65nm integrated circuits is to assure the wafer to wafer repeatability.

Particularly in plasma processes etching for IC fabrication, with metal gate, organic or metallic residues are deposited on the chamber walls. Because of the deposition of these layers a large and uncontrolled shifts in the etch process could be observed. To avoid this problem dedicated dry cleaning of the etching chamber must be developed but this methodology requires the precise knowledge of the layer coated on the reactor walls (1). This is not easy because of complexity of the stacks that need several steps of etching with different chemistries. Particularly the sharing of the equipments among many different process increases the complexity of layer coated. In order to assure that every wafer has been etched correctly a real-time monitoring of plasma impedance has been developed. The experiments were performed in a low pressure inductively coupled plasma reactor supplied with 13.56 MHz rf powers. Through the monitoring of dedicated equipment parameter tightly related to the plasma impedance is possible to active a dedicated fault detection control. During the wafer process, the check of this parameter along dedicated step that use only oxygen, it is possible to get the status of chamber wall in real-time; therefore is possible to activate a recovery action if necessary and don't process any other wafer. In order to validate the correlation between equipment parameter and reactors wall status etch rate test and XRF spectroscopy tests were performed. The innovation of this method consists therefore in the possibility to directly estimate the state of chamber walls during the process without having to affect measures devoted through sample (2).

(1) R. Ramos, G. Cunge and O.Joubert. J.Vac. Sci. Technol. B 26(1), Jan/Fab 2008

(2) O.Joubert, G. Cunge, BPellisier , L. Vallier, M. Kogelschatz and E. Pargon. . J.Vac. Sci. Technol. A 22(3), May/Jun 2004