| AVS 58th Annual International Symposium and Exhibition | |
| Plasma Science and Technology Division | Thursday Sessions |
| Session PS-ThM |
| Session: | Neutral Beam and Low Damage Processing |
| Presenter: | Yoshinori Nakakubo, Kyoto University, Japan |
| Authors: | Y. Nakakubo, Kyoto University, Japan A. Matsuda, Kyoto University, Japan M. Fukasawa, Sony Corporation, Japan Y. Takao, Kyoto University, Japan T. Tatsumi, Sony Corporation, Japan K. Eriguchi, Kyoto University, Japan K. Ono, Kyoto University, Japan |
| Correspondent: | Click to Email |
Plasma-induced Si substrate damage has become one of the critical issues in advanced MOSFETs with shallower junction in source/drain extension (SDE) regions, since the damaged layer thickness will be in conflict with the device design margin (e.g. ~ 5 nm in 32-nm technology node). This damage causes the device performance degradation by forming Si loss (Si recess structure) [1]. Ohchi et al. have reported that the damaged layer by hydrogen-containing plasma is thicker than that by plasma without hydrogen, resulting in deeper Si recess [2]. Eliminating the damaged layer by wet etch and reconstructing the crystalline structure by thermal processes are strongly required, but there have been few studies on these issues. In this study, we report the effect of rapid thermal annealing on the damaged layer by HBr/O2- and H2- plasmas.
P-type silicon substrates with thermal-oxide layer (2 nm) were exposed to the capacitively coupled plasma (CCP) by applying a dual bias frequency (60/13.56 MHz). HBr/O2 and H2 gases were used. Damaged samples were cleaned by the dilute-HF solution (DHF) for 2 min before rapid thermal annealing (RTA) at 1035 °C for 10 s in a N2 gas ambient. The structure and the electrical conductivity were identified using spectroscopic ellipsometry (SE) and current-voltage (I-V) measurement, respectively. Capacitance-voltage (C-V) method was performed to analyze the features of the defect site in the damage samples.
Although all the damaged samples after RTA had a thicker oxide layer (~ 1.4 nm) compared with that of the native oxide layer (~ 0.6 nm) grown on the Si surface treated by SC2, a much higher current through the thick oxide (~ 20 mA at -0.1 V) was observed in comparison with that through the native oxide (~ 0.7 mA at -0.1 V). This feature is due to the nitrided Si that may be assigned by SE. This nitirided layer was found to be difficult to remove (etch) even by the DHF-treatment of several minutes, and thus the damaged MOSFETs may suffer from performance degradation by the presence of the nitrided layer. These findings imply that in the case of H-plasma, the process recipe for RTA targeted to cure the plasma-induced Si damage should be carefully optimized.
[1] K. Eriguchi et al.: IEEE Electron Dev. Lett. 30 (2009) 712.
[2] T. Ohchi et al.: Jpn. J. Appl. Phys. 47 (2008) 5324.