Paper PS-MoM6
Study of Metallic Interfaces Etching for High-K Metal Gate stacks in CMOS 28 nm Technology

Monday, October 31, 2011, 10:00 am, Room 201

In CMOS technology, the downscaling of the transistor gate dimension, driven by ITRS roadmap specifications for advanced technology, requires the introduction of new materials. Dry etching step of those new “High-K Metal Gate” (HKMG) stacks is critical for the electrical performances of the devices and needs very accurate process control to achieve correct profiles, with a good Critical Dimension control. Moreover, characterization tools are now dealing with thin materials thicknesses sometimes around the limit of one full atomic layer. In this work we focus on dry etching process of 28nm technology High-K Metal Gate stacks. Several issues, especially for Metal/Capping layer interfaces, are investigated to better understand and control physicochemical interactions.

Most of etching experiments are carried out in a 300mm DPS AdvantageEdge^TM etch chamber from Applied Materials allowing in situ diagnostic, as reflectometry and spectroscopic ellipsometry. This modified tool permits to transfer wafer under vacuum to a customized Theta 300 XPS system from Thermo Fisher Scientific for quasi in-situ analysis without exposure to the environment. Samples were 300mm diameter Si wafer with full sheet and/or patterned deposited layers. Industrial 28nm photolithography & plasma etching process developed to gate first approach were employed.

Preliminary experiments have shown that foot and undercut effects are possible profiles deformations due to metallic interfaces, and we have to control these deviations.

Consequently, we focused first on the TiN/LaO interfaces which we highlight as a critical step. TEM analyses demonstrate that LaO capping layer acts as etch stop layer for current TiN etching chemistries. Therefore, a specific step for LaO removal is needed; otherwise etching residues are left over.

Layer thickness and step time in the specific removal of Lanthanum oxide are some parameters which directly impact the under-layer materials with the observation of pitting on nMOS open areas or residues on pMOS.

XPS characterizations were carried out. Etching results analyses for TiN/LaO/TiN interface reveal the fact that after the whole stack etching step, some LaO residues remain on the sample surface although TiN disappear as evidenced from XPS survey scan. The conclusion is that TiN looks totally removed as Lanthanum can be redeposit or for certain push-forward. Such as mechanisms were considered, and experiments were carried out to understand and complete this result.

Integration of thin metallic and capping layers in gate stacks challenge dry etching process. Those results highlight the trend of interactions all across the plasma etch process.