Paper PS+SE-MoA3
193nm Photoresist Pre-Treatments Before Plasma Transfer to Improve LWR Transfer and CD Control

Monday, October 31, 2011, 2:40 pm, Room 201

Linewidth roughness (LWR) is today one of the main parameters that limits our ability to shrink the transistor gate dimension down to 20nm. Indeed, LWR needs to be controlled down to 2nm to ensure good electrical performance of the future CMOS device, while state of the art patterning techniques only allows 4-3 nm gate LWR at best. The major issue in decreasing the gate LWR comes from the fact that the significant LWR of the resist pattern printed after 193nm lithography (about 6nm measured by CDAFM) is transferred into the gate stack materials during the subsequent plasma etching processes. One way to minimize the final gate LWR is to apply various pre-treatments to the resist patterns obtained right after lithography (before any plasma pattern transfer step).

In the present study, we have used CD-SEM and CD-AFM techniques to investigate the impact of different types of resist pre-treatments (combining plasma exposure (HBr, Ar, H₂ plasmas), vacuum ultra violet (VUV) light exposure, and annealing) on the photoresist LWR and profile. Many characterization techniques (FTIR and Raman spectrometries, ellipsometry, chromatography, DMA, TGA) have also been used to characterize the physico-chemical modifications of photoresist films responsible for the resist smoothening. We have also investigated the benefits of those resist pre-treatments on both LWR and CD control after pattern transfer in different stacks of materials.

We will show that all treatments generate resist chemical modifications that lead to a decrease in resist LWR while the etch resistance is not always improved. All treatments have in common the cleavage of the side groups (lactone group for plasma treatment and protecting group for annealing treatment) and a decrease of the glass transition temperature that seems to have a direct impact on the LWR decrease. But some other mechanisms compete according to the treatment used and its duration: main chain scission and crosslinking, leading to some different etch resistance improvement. Consequently even if some specific treatments (VUV light exposure, annealing) can improve the resist LWR before transfer, the subsequent plasma etching steps can degrade it and also induce a loss of CD control. We will show that by combining plasma exposure and annealing treatment the photoresist LWR could be decreased down to 2.6nm and that this LWR could be transferred into polysilicon gate without LWR and CD degradation.