Paper PS+SE-MoA10
Sub-32nm Node Mask Patterning for Deep Silicon Trench Etch

Monday, October 31, 2011, 5:00 pm, Room 201

In the last several semiconductor device generations, one of the complexities in fabricating ever smaller feature sizes and increased density, has been the stringent requirements placed on photolithographic processes and mask scheme formation. The use of Immersion Lithography, reduced resist layer thicknesses and planarity requirements have driven the need for complex multilayer-multimaterial stacks that can be utilized for subsequent plasma Etching masks.

One requirement by manufacturers of Sub-32nm DRAM technology, utilizing deep silicon memory cells, is an extremely high aspect ratio mask that enables the anisotropic etch profile of the Silicon Trench. To meet both the needs of the photolithographic processes and the high aspect ratio mask requirements of the Silicon Trench etch, a complex Photo Resist, Silicon Anti-reflective coating, Optical Dispersive Layer, CVD Oxide layer is used. This deposited mask stack also sits on top of a Silicon-on-Insulator layer that must also be etched through anisotropically.

In this paper, we describe the unique requirements of etching each film stack in order to meet the overall physical requirements of this high aspect ratio mask patterning etch. It also describes the process capabilities of a commercially available Capacitively Coupled Plasma reactor that enables it to meet these advanced complex film stack requirements.

This work was performed by the Research and Development team at TEL Technology Center America in joint development with IBM Semiconductor Research & Development Center.