Paper PS1-TuM3
Feature Scale Model of Shallow Trench Isolation (STI) Etch in HBr Plasma and Comparison with Experiments

Tuesday, October 19, 2010, 8:40 am, Room Aztec

Continued scaling in the semiconductor industry provides new challenges for critical etch applications in front-end logic and memory devices. As device sizes shrink, control of Shallow Trench Isolation (STI) features to create active area islands become more important. Typical logic STI performance metrics for a 300mm wafer include trench angle, trench depth and iso-dense depth loading and their corresponding within-wafer uniformity. In addition to these metrics, memory STI application includes a challenging requirement for intra-cell depth loading that arises due to within-feature variation of the space critical dimensions (CD) in the dense feature array. These stringent profile control requirements are typically met by operating halogen-based Transformer Coupled Plasma (TCP™) in the mid-pressure operating regime.

This paper will discuss the semi-empirical feature scale model of STI etch in HBr plasma to address iso-dense and intra-cell trench depth loading for an etch stack representative of memory STI features. Plasma diagnostics and reactor-level models are implemented to characterize the HBr plasma produced in the TCP configuration process chamber. Kinetic parameters in the model are constrained by matching simulated feature profiles with those experimentally obtained at various process conditions that are a subset of the process space of interest. The feature scale model is quantitatively calibrated to the experimental profiles and validated for prediction within the process space. The validated profile simulator is used to identify reactor-level process knobs that minimize iso-dense and intra-cell depth loading. The advantages of calibrated process-specific profile simulation in enabling efficient exploration of parameter space during process development and future challenges facing STI trench depth etch will be discussed.