The scaling of CMOS transistors to 20nm and beyond may invoke utilization of materials that are far different in electrical and mechanical properties from conventional silicon. InGaAs, InP, GaAs are examples of such materials being considered for future device fabrication and as such will present numerous challenges for etch. These include balancing profile needs against stringent selectivity and scalability requirements to address the myriad of device needs at this node. Etch characterization of these materials using various processing chemistries (Cl2, CH4, H2), tool conditions (chuck temperature, power, bias, pressure) and tool types, as well as a variety of material stacks has been carried out using 3-4” wafers. GaAs and InGaAs etch rates of ~40-45A/s at high chuck temperature of 225 degrees are obtained for 30nm lines spaced at 1-50um. A linear relationship between etch rate and temperature is also observed with H2/Cl2 chemistry. Chuck temperature impact on trench/ line profiles is understood on the basis of volatility of the byproducts as well as on the nature of the resulting sidewall passivation. Data showing the difficulties in pitch scaling and controlling etch rates of stacked materials will also be discussed.