Paper PS1-TuA7
Challenges in sub-100nm Dual Damascene Etch of Porous Oxycarbosilane Ultra Low-k Dielectrics for BEOL Integration

Tuesday, October 19, 2010, 4:00 pm, Room Aztec

There has been much interest recently in porous oxycarbosilane (POCS)-based materials as the interconnect layer dielectric (ILD) in back-end-of-line (BEOL) manufacturing due to their superior mechanical properties compared to conventional porous SiCOH at equivalent porosity and dielectric constant. [1-4] While it is well known that plasma etching and ashing processes can cause significant damage to porous ultra-low k dielectric materials in general, little has been reported about the effect of plasma damage to POCS as the ILD material. In this work, we discuss the effect of plasma etching and ashing processes on POCS during the fabrication of single and dual damascene structures for BEOL integration. We used TEM-EELS to quantify chemical composition changes at the top, bottom, and sidewalls of POCS trenches after each plasma etching and ashing step. After plasma processing, POCS structures undergo extensive plasma damage such as pitting, microtrenching, and the generation of trench bottom roughness. Opening of the cap layer exacerbates these etch damage features. Damage is reduced by increasing the neutral-to-ion ratio of the gas discharge in the ULK trench etch and eliminating O₂ from the ashing process. The use of vapor phase silylation between etch process steps is also shown to repair plasma-damaged POCS. However, we show that the most significant improvement to post-plasma damage occurred by reducing the pore size of the starting POCS material while maintaining comparable porosity, i.e. dielectric constant.

[1] W. Volksen, et al., Chem. Rev. 110, 56 (2010).

[2] G. Dubois, et al., J. Of Sol-Gel Science and Technology 48, 187 (2008).

[3] G. Dubois, et al., in Dielectric Films for Advanced Microelectronics, edited by M. Baklanov, et al., (Wiley, New York, 2007), p. 33.