Every technology node brings new processing challenges. The etching of low-k and ultra-low-k (k=2.4 and below) materials that are currently used in leading edge interconnects is very demanding. With a porosity varying from ~15 to 30%, the films are easily damaged during the various processing steps and it is easy to have undesired film modifications (physical defects, collapse, impurity penetration, roughening of the surfaces, moisture uptake…) that degrade interconnect reliability and performance.

 

In this talk we will present recent work done on optimization of dielectric etching using CF3I, a promising replacement gas for CF4 in interconnect etch applications. Using a Design of Experiment (DOE) approach through a Taguchi-like Method combined with the capabilities of a State-of-the-Art Unaxis 200mm wafer etch system, the influences of the key parameters on the etching mechanism and performance will be presented. The DOE approach is introduced here to minimize the number of experiments while maximizing the process understanding. For instance, one of the results of the experimental matrix suggests an etching rate contribution of CF3I that is non-linear. In addition to characterization of etch rate, the samples are characterized using RBS, AES and SEM to fully understand the impact of the process parameters on overall film quality. Baseline data as well as structure patterning will be presented after the optimization process using CF3I alone and also using CF3I mixed with well established fluorocarbons.