Paper PS1-TuA11
Achieving Lithographically Independent sub-35nm Vias for Phase Change Memory Applications

Tuesday, October 19, 2010, 5:20 pm, Room Aztec

Non-volatile phase change based memory has recently garnered significant interest due to its potential for scalability beyond that of conventional DRAM and Flash memory technologies.[1] However, multiple etch challenges exist in the fabrication of robust PCM devices and not all have been thoroughly discussed and/or researched. For instance, patterning of the novel phase change material without causing material modification and performance degradation is a well known issue and has been reviewed in the past.[2,3,4] On the other hand, the ability to fabricate robust and uniform sublithographic contacts (to the phase change material) is rarely discussed from an etch perspective. In this presentation, this latter issue is explored in detail and a lithographically independent etch process scheme with the capability of yielding sub-35nm vias is presented. Critical factors such as oxide and nitride etch selectivity, taper angle and etch stop phenomenon are all reviewed. Lastly, the application of this method for logic applications such as gate contacts and BEOL via patterning will also be discussed with a focus on the ultimate scaling limitations of this process.

[1] Y.C. Chen, C.T. Rettner, S. Raoux et al., IEDM Tech. Dig., p. S30P3, 2006.

[2] P. Petruzza, Paper PS-MoA4, AVS 54th International Symposium, 2007

[3] E. A. Joseph, T. D. Happ, S.-H. Chen, S. Raoux, et al., Symp. VLSI-Technology Systems and Applications, 2008. pg 142-143, 2008

[4] E. A. Joseph, S. Raoux, J. L. Jordan-Sweet, D. Miller, H-Yu Cheng, A. Schrott, C-F. Chen, R. Dasaka, B. Shelby, Y. Zhang, C. Lam, J. Washington, G. Lucovsky and M. Paesler, Paper PS1-ThM11, AVS 56th International Symposium, 2009