Paper PS1-TuA10
Ultra-high Selectivity Silicon Nitride Liner Etch: Mitigating Substrate Damage in Logic-based Contact Level Interconnects

Tuesday, October 19, 2010, 5:00 pm, Room Aztec

Reactive Ion Etch [RIE] of Silicon Nitride films, utilized primarily as spacers, hard masks or etch stop layers [ESLs], is pervasive throughout logic and flash microelectronics fabrication processes. While the most critical RIE-related specifications vary widely depending on the specific application and photolayer, contact level liner/ESL removal is among the most challenging. This application ideally requires high etch selectivities to multiple material types [including NiSi, SiO₂, Si, and Si_xGe_y] at the bottom of a high aspect ratio feature where etch stop marginality in a polymer rich regime can impact opens yield. Furthermore, relying on high radical density, low ion energy, primarily chemical etch processes utilized for Si_xN_y type spacer applications often lack profile control where sidewall bowing can result in metallization related yield fallout.

This work characterizes a new contact RIE process developed for 28nm and beyond technology nodes. Reported is the successful integration of an ultra high selectivity Si_xN_y liner removal process [> 40:1 in hole selectivity for Si_xN_y : Si]. Cross-sectional characterization of contact profile and in hole selectivity data will be provided. High Opens/Shorts yield [equal or better than baseline] as determined by voltage contrast metrology and inline E-Test will be shown. In addition, a 10x reduction in gate leakage will be shown based in-line E-Test attributable to reduced active area Si loss/recess.