AVS 57th International Symposium & Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS1-MoA

Paper PS1-MoA9
Plasma Etching Challenges for Patterning Advanced Gate Stacks for 22nm Node and Beyond

Monday, October 18, 2010, 4:40 pm, Room Aztec

Session: Advanced FEOL / Gate Etching I
Presenter: Y. Zhang, IBM T.J. Watson Research Center
Authors: Y. Zhang, IBM T.J. Watson Research Center
S.U. Engelmann, IBM T.J. Watson Research Center
Q. Yang, IBM T.J. Watson Research Center
R.M. Martin, IBM T.J. Watson Research Center
E.A. Joseph, IBM T.J. Watson Research Center
M.A. Guillorn, IBM T.J. Watson Research Center
E.M. Sikorski, IBM T.J. Watson Research Center
W.S. Graham, IBM T.J. Watson Research Center
B.N. To, IBM T.J. Watson Research Center
N.C. Fuller, IBM T.J. Watson Research Center
Correspondent: Click to Email
There are increasingly more challenges facing by patterning advanced gate stacks due to continuously scaling of CMOS device dimensions to 22 nm node and beyond. The major causes are from the following: (1) new materials being introduced for advanced gate stacks to enable continuously scaling of Tinv; (2) continuously shrinking of pitch and higher density; (3) complex gate patterning integration schemes, such as double or multiply exposures and double or multiply etching with multiply layer mask schemes due to the delay of EUVL; (4) 3D active area and gate structures, such as finFET, tri-gate, Si nanowire (SiNW) FET, etc.; and (5) move to the deep-nanometer regime, such as ETSOI with < 5nm Si channel. The 3D structures with the combination of novel materials and sub-50nm pitches for gate stacks impost unique challenges and demands on plasma etch process technology and news integration schemes and plasma etch tooling innovations. To meet all the requirements of target pitches, device feature profile, line edge roughness (LER) or line width roughness (LWR), and device performance/functionality, Different and unconventional approaches have to be introduced in plasma etching processing to fabricate 3D fins/active area, gates and spacers, particularly with the use of metal/high-k dielectric gate stack materials. Recent results illustrating some of these etching challenges including the progresses developed aiming on improving 3D profiles and achieving increased control of LER/LWR for fin, gate and spacer structures will be presented.