Paper PS1-MoA8
Advanced Gate Patterning of Novel Multi-Gated Devices for 15nm Node and Beyond

Monday, October 18, 2010, 4:20 pm, Room Aztec

To continue scaling CMOS devices at the traditional pace following Moore ’s law, Short Channel Effects (SCE) are the major issues limiting the use of planar device geometries for future technology nodes. Alternative device integration schemes are currently being tested to test the impact on SCE and extend technology nodes even further. The device candidates that are currently being tested include planar devices, FinFETs, Trigates and Nanowires (gate all around device). The gate formation on these advanced, multi-gated devices imposes completely new challenges on the plasma etch conditions, which translates to the demand to control the plasma process in a second (and a third) dimension. E-beam lithography has been proven to be a very valuable tool to explore plasma processing at device sizes unattainable by state-of the art optical lithography. We have demonstrated the fabrication of gates above a Fin of varying dimensions of gate and fin for SRAM cells down to 0.025um². Significant challenges for this integration lie in the gate as well as the spacer formation, while maintaining the Si fin that has no hardmask to prevent plasma damage. While maintaining a vertical gate profile, no Silicon loss was observed on the Si Fin. A more significant challenge is the spacer formation, where Nitride needs to be removed from the fin sidewall, while maintaining it on the gate sidewall to prevent device shorts. An even higher degree of process control is needed in the fabrication of nanowire or gate all around devices. Maintaining a vertical gate profile while not damaging or destroying nanowires of diameters less than 5nm is critical. A gate recess process was employed to release the nanowire structures. A highly selective spacer rie process was developed to yield nanowires down to 3nm in diameter.