Suppression of Si substrate damage caused by energetic ion bombardment is one of the most critical issues in advanced devices. Si substrate damage during gate electrode etching causes the “Si recess” structure, which is reported to degrade device performance. In previous work, we developed a bilayer model (surface oxide/dislocated Si) of the damaged layer and studied monitoring methods. In this paper, we have investigated the damage generation by plasma exposure and the removal of damage by wet treatment. We have also studied the impact of the damage on electrical performance. A dual frequency (60/13.56 MHz) CCP reactor was used in this study. A SiO₂ layer (1.7 nm) was formed on the Si substrate and exposed to HBr/O₂, H₂, and O₂ plasma. The pressure and Vpp were kept constant at 60 mTorr and 420 V. Diluted HF (100:1) was used to perform a wet treatment. The Si substrate damage was analyzed by spectroscopic ellipsometry (SE), HRBS, and TEM. In the SE analysis, data was fitted using a four-layer model (ambient/SiO₂/dislocated Si/substrate). Dislocated Si was modeled as a mixing of SiO₂ and polysilicon. C-V characteristics were measured with a mercury probe system. HBr/O₂ plasma generates a thicker surface oxide layer than O₂ plasma. The root cause of the thick oxide layer is enhanced diffusion of oxygen in the dislocated Si layer generated by deep penetration of H⁺ from the plasma. The thickness of the oxide layer (T_ox) increased monotonically with increased exposure time (t) and reached about 10 nm at 600 s. The T_ox was found to depend on t^1/2, which is a so-called parabolic relationship (diffusion-controlled oxidation) in the Deal-Grove model. The T_ox and the thickness of the underlying dislocated Si layer (T_d) were compared by SE, HRBS, and TEM. The results were quite consistent across all analyses. The T_ox and T_d after dHF treatment were also analyzed. The surface SiO₂ was completely removed and the upper part of the dislocated Si was also eliminated (generation of Si recess). As the remaining dislocated Si was mainly caused by H⁺ ion penetration, the C-V characteristics for H₂ plasma-exposed samples were analyzed. A negative bias voltage shift was observed, which implies the generation of positive charge trapping in the interface between the surface oxide and the dislocated Si layer. To minimize the Si damage during gate etching, it is necessary to control the H⁺ penetration depth within the thickness of the thin gate oxide by controlling the IEDF precisely. Thus, quantitative control of the IEDF, precise monitoring of surface structure, and understanding the effects on device performances are indispensable for creating advanced devices.