The continuous shrinking of CMOS device node have put stringent requirement on reducing plasma induced damage and under layer film loss during dry etch. It is always almost the case that when a film is etched in a plasma the under layer film sustains some extent of damage and in some cases this film is etched leading to recess. Up until now this was within the noise to some extent, but beyond 22nm technology node this will be critical in defining device performance. Si roughness and recess during FEOL etch (like gate and spacer) results in degradation of device performance; like shift in threshold voltage, high leakage current leading to increased power consumption. These are some of the roadblocks in achieving high device performance at high packing density. Therefore, it is desirable to attain infinite selectivity between the film that is intended to be etched and its underlying film such that the under-layer film is damage free. In many cases strategies to control Si damage leads to tradeoffs like tapered profile which is not acceptable. This talk will discuss some of the issues in controlling Si damage in FEOL applications and some interesting results.