AVS 57th International Symposium & Exhibition
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeM

Invited Paper PS-WeM9
Modeling of Plasma-Induced Damage and Its Impacts on Parameter Variations in Advanced Electronic Devices

Wednesday, October 20, 2010, 10:40 am, Room Aztec

Session: Plasma Surface Interactions (Fundamentals & Applications) I
Presenter: K. Eriguchi, Kyoto University, Japan
Correspondent: Click to Email

With scaling of advanced electronic devices, plasma-induced damage (PID) has been investigated extensively from various viewpoints. Although suppressing PID is one of the critical issues in plasma process optimization, there have been few reports which correlate the plasma parameters to device performance in terms of PID.

This study discusses one of the PID mechanisms, physical damage induced by ion bombardment on Si surface. We propose a new comprehensive framework linking an ion energy and the distribution function to device parameters, i.e., a unified PID design.1) The framework is based on a modified range theory2) and an analytical device-degradation model.3),4) To verify the validity, we performed both experiments to clarify the damaged-layer structures (the thickness, defect site density, and the electrical properties) by novel techniques5) and simulations (molecular dynamics and device simulations) to understand the quantitative effects.

We demonstrate prediction of performance degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs) damaged by an inductively coupled plasma reactor which can apply the bias with two different frequencies (400 kHz and 13.56 MHz). The model prediction indicates that, in typical etching processes, the damaged-layer thickness can be determined primarily by an average self-dc-bias voltage rather than applied bias frequencies. This implication is found to be in good agreement with experimental results. Moreover, one can estimate also variation in device parameters from basic plasma parameters. Thus, it is concluded that the proposed framework is a key concept for future process and device designs.

1)K. Eriguchi et al., IEDM Tech. Dig. (2008) 443.

2)K. Eriguchi et al., to be published in Jpn. J. Appl. Phys., 2010.

3)K. Eriguchi et al., Proc. Symp. Dry Process (2009) 267.

4)K. Eriguchi et al., IEEE Electron Device Lett. 30, 1275 (2009).

5)K. Eriguchi et al., Jpn. J. Appl. Phys. 47 (2008) 2446.