| AVS 57th International Symposium & Exhibition | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS-TuP |
| Session: | Plasma Science and Technology Poster Session |
| Presenter: | J.K. Yeon, Sungkyunkwan University, Republic of Korea |
| Authors: | J.K. Yeon, Sungkyunkwan University, Republic of Korea W.S. Lim, Sungkyunkwan University, Republic of Korea Y.Y. Kim, Sungkyunkwan University, Republic of Korea B.J. Park, Sungkyunkwan University, Republic of Korea G.Y. Yeom, Sungkyunkwan University, Republic of Korea |
| Correspondent: | Click to Email |
As the critical dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) shrinks to 45 nm and below, conventional poly silicon gates on ultrathin SiO2 dielectric layers need be replaced by metal gates on high-k dielectric materials. However, the successful adoption of these new materials imposes new integration problems. Among many integration issues, selective etching of metal gate electrodes and the high-k gate dielectrics over the Si substrate is expected to be one of the critical steps in the process integration of the front end of the line. In the case of TiN etching on HfO2 layer using conventional RIE etching, HfO2 layer can be electrically damaged by charged particle leading to higher leakage current, the change of threshold voltage, etc. In order to solve these problems, in this study, we investigated etch characteristics of TiN on HfO2 layer using low angle forward reflected neutral beam and compared with those by conventional RIE etch process.
As a result, we observed nearly unlimited etch selectivity of TiN/HfO2 uisng HBr/Cl2 gas mixing neutral beam by controlling energy (<100 eV). Also, using TEM and AFM, we observed an anistropic etch profile and smooth surface roughness (0.109 nm). Neutral beam for metal gate etching process turns out to be very promising for gate/high-k dielectric complementary MOSFETs due to lower interface trap generation during etching process.