| AVS 57th International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoM |
| Session: | Advanced BEOL / Interconnect Etching I |
| Presenter: | Y. Yin, IBM Systems and Technology Group |
| Authors: | Y. Yin, IBM Systems and Technology Group J.C. Arnold, IBM Systems and Technology Group M. Colburn, IBM Systems and Technology Group S. Burns, IBM Systems and Technology Group S. Holmes, IBM Systems and Technology Group C. Koay, IBM Systems and Technology Group R. Kim, Global Foundries G. Landie, STMicroelectronics D. Horak, IBM Systems and Technology Group Y. Mignot, STMicroelectronics H. Tomizawa, Toshiba Corporation |
| Correspondent: | Click to Email |
As feature critical dimension (CD) shrinks towards and beyond the 22nm node, limitations of traditional patterning processes become critical. Conventional 193nm immersion lithography is not able to resolve trenches below 40nm half pitch with a single exposure. Patterning vias at appropriate CD and spacing is equally challenging. Extreme ultraviolet (EUV) lithography offers appropriate k1 reduction to solve these problems, but the equipment and metrology infrastructure is not in place to support 15nm node development on a large scale. Thus, much of the industry's attention is being paid to double patterning techniques based on existing 193nm imaging capability. In this paper, we will discuss various double patterning schemes and the associated technical challenges for plasma etching - both for generating patterns with sub-40nm half pitch and for utilizing the resultant masking stacks for BEOL etching. In particular, we will review the issues associated with applying "double-exposure double-etch" sequences, "double-exposure single-etch" approaches, and sidewall image transfer to formation of dual-damascene structures in advanced ultra low-k dielectrics.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.