Paper PS-MoM4
RIE Process Challenges in sub 30nm node Trench First Metal Hard Mask Scheme

Monday, October 18, 2010, 9:20 am, Room Aztec

As scaling of microelectronic devices approaches sub 30nm nodes, many material and module process challenges in BEOL plasma patterning have been reported. One of the methods that has gained traction over recent years for enabling sub 20nm feature patterning is the Trench First metal Hard Mask (TFmHM) scheme. While this scheme solves or mitigates many challenges that are inherent with Via First Trench Last (VFTL) Scheme, it introduced other dielectric RIE process and hardware challenges. One of the root causes of the former is the fact that all patterns and materials are exposed to plasma at the same time. As such, the simultaneous control of via, trench and chamfer profiles (i.e. Critical Dimensions, depth, taper profile, etc), the need to control selectivity between multiple patterning layer (TiN, TEOS, ULK, Barrier cap, etc), and ULK damage control has become more pertinent in the dielectric etch. As the direct result of such tight process guidelines, the hardware challenges arise and new dimensions in process controls are needed. The prolonged exposure of the TiN to the plasma created the need for more robust production worthy hardware. The required selectivity of the materials necessitate temperature controllable chucks. The more complex patterning techniques require ULK preservation and other uniformity controls. In this paper, the RIE efforts on process controls of the profiles, material selectivity, associated hardware challenges and possible future roadmaps under TFmHM scheme will be discussed.

This work was performed by the Research team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY.