| AVS 57th International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoM |
| Session: | Advanced BEOL / Interconnect Etching I |
| Presenter: | N. Posseme, CEA-LETI-MINATEC, France |
| Authors: | N. Posseme, CEA-LETI-MINATEC, France T. Chevolleau, CNRS-LTM, France T. David, CEA-LETI-MINATEC, France M. Darnon, CNRS-LTM, France F. Bailly, STMicroelectronics, France R. Bouyssou, STMicroelectronics, France J. Ducote, STMicroelectronics, France C. Verove, STMicroelectronics, France O. Joubert, CNRS-LTM, France |
| Correspondent: | Click to Email |
The choice of copper/Low-k interconnects architecture is one of the keys for integrated circuits performances, process manufacturability and scalability. Today, the implementation of porous low-k material becomes mandatory in order to minimize the signal propagation delay in the interconnections. In this context, the traditional plasma processes issues (the plasma-induced damages, dimension and profile control, selectivity) and new emerging challenges (sidewalls surface roughness, dielectric wiggling) become the critical points to control the reliability and defectivity.
Based on plasma-surface interaction understanding, the main issues and also the potential solutions will be illustrated through different process architecture using metallic or organic hard masks strategies.