AVS 57th International Symposium & Exhibition
    Plasma Science and Technology Wednesday Sessions
       Session PS+MN-WeM

Paper PS+MN-WeM9
Key Challenges in Extremely High-Aspect- Ratio Dielectrics Etching at 3x nm DRAM and Beyond

Wednesday, October 20, 2010, 10:40 am, Room Galisteo

Session: Plasma Processing for 3D Integration, TSV, and MEMS
Presenter: S.K. Lee, HYNIX Semiconductor Inc., Republic of Korea
Authors: S.K. Lee, HYNIX Semiconductor Inc., Republic of Korea
J.-H. Sun, HYNIX Semiconductor Inc., Republic of Korea
S.O. Lee, HYNIX Semiconductor Inc., Republic of Korea
J.-S. Bang, HYNIX Semiconductor Inc., Republic of Korea
S.-I. Lee, HYNIX Semiconductor Inc., Republic of Korea
C.-M. Lim, HYNIX Semiconductor Inc., Republic of Korea
S.-Y. Kim, HYNIX Semiconductor Inc., Republic of Korea
D.-G. Lim, HYNIX Semiconductor Inc., Republic of Korea
S.-K. Park, HYNIX Semiconductor Inc., Republic of Korea
J.-G. Jung, HYNIX Semiconductor Inc., Republic of Korea
Correspondent: Click to Email
One of key issues in fabricating the dynamic random access memories (DRAM) is to control the vertical profile effectively during the etching of a SiO2 high aspect ratio contact holes (HARC). In order to ensure acceptable Cs (>25fF/Cell) for DRAM at half pitch (HP) 3x nm and beyond generation, it is required of fabricating cell capacitors having very highly aspect ratio above 50:1. Thus, the HARC etching technology to get smaller bowing width as well as larger opening area becomes the most difficult challenges among numerous DRAM fabrication steps. This is because of trade-off between both bowing and opening requirement during HARC etching. Although the mechanism of bowing and not-opening has reported in several studies at above 70nm technology nodes, still has not yet been reported at hp 3x nm and beyond. In this presentation, especially, we will focused on the HARC etching issues at Nitride Fence supported Capacitor (NFC) scheme which is used to prevent leaning. Capping is arose by several factors, which reduce the etch rates and cause the contact opening failure, then eventually affects on the electrical characteristics. The types of capping studied in this work can be divided into three categories as the etching proceeded, such as polymer pinch-off, excess polymer capping originating from polymer rich chemistry at top region, and non-steady polymer deposition and removal at etch front. In this study, we investigated that capping issues become more serious when 2MHz range power is added to increase contact opening margin. To avoid these types of different failures aforementioned, it is necessary to understand the plasma etching behavior at hp 3x nm and beyond compared to previous technology nodes. In addition, beyond typical bowing position, an additional bowing position at NFC is also key concern issues within oxide layer between hard mask (HM) and Nitride from the wafer top surface. This is caused by the ions scattered from the mask side-wall slope on the contact-hole. It can be reduced effectively by adjusting HM material, thickness, and etching conditions. Especially, HARC etching parameters also play an important role to suppress the bowing and capping. We will report here how contact hole’s opening and bowing are enhanced, and how they can be controlled by adjusting etching conditions also. It is suggested that optimizing the etching condition with a suitable concept in this work would be the most effective solution during the HARC etching process. Consequently, Key approaches on HARC etch processes for fabricating of a contact hole in SiO2 with aspect ratios of 50:1 and beyond were evaluated in this work in detail.