As the critical dimension of metal-oxide-semiconductor field-effect transistor shrinks less than 45 nm and below, conventional polysilicon gates on ultrathin SiO2 dielectric layers should be replaced by metal gates on high-k dielectric materials. However, the adoption of these new materials imposes new integration problems. Among many integration issues, the etch selectivity of the etched layers (metal electrode or high-k dielectrics) to the under-layers (high-k dielectrics or Si substrate) is one of the most important issues in the patterning of the gate stack structures.

In order to solve these problems, in this study, we applied two step etch process where, the metal gate electrode is selectively etched using a reactive neutral beam against a high-k dielectric layer and then the high-k dielectric layer is removed using atomic layer etching (ALET) for precise etch depth control.

The result showed nearly infinite etch selectivity of TiN/HfO2 using a HBr/Cl2 neutral beam by controlling energy (<100 eV). In addition, an anistropic etch profile and smooth surface roughness (0.109 nm) could be observed using TEM and AFM. For the ALET of HfO2, the monolayer etching condition of 1.2 Å /cycle could be observed using BCl3 ALET and, after the 30 etch cycles, exactly 3.5nm thick HfO2 layer was removed with a low surface roughness and without the change of surface composition. When we compared the properties of MOSFET devices fabricated using conventional RIE processing and those using the neutral beam/atomic layer etching, the improvement of characteristics of NMOSFET and PMOSFET could be observed for the devices fabricated using neutral beam /atomic layer etching.

 

 ACKNOWLEDGMENT

This work supported by the National Program for Tera-Level Nano devices of the Korea Ministry of Education, Science and Technology (MEST) as a 21st Century Frontier Program.