Invited Paper PS1-TuM1
Inductively-Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Advanced Gate Etching

Tuesday, November 10, 2009, 8:00 am, Room A1

The pace at which microelectronics technology is progressing is highly challenging with conventional device architecture. The stringent and conflicting requirements in microelectronics for damage-free plasma etching processes, with improved uniformity, higher selectivity, better anisotropy, more precise ion energies/fluxes control and enhanced process throughput have stimulated an intensive research effort among academic and industrial communities. This research is focused on novel approaches for the design/control of the next generation of plasma processing reactors. Following the above challenges, the dry etch process regime for gate etching has moved towards low pressure plasmas with higher densities. In this regime, the risk of plasma induced damage(PID) or charging damage increases, potentially affecting the overall device electrical performance. PID includes UV damage and highly energetic ion bombardment damage. Moreover, for high aspect ratio structures, electron shading effect becomes more dominant enhancing the risk of charging damage. In the past, it was demonstrated that pulsed radio frequency(PRF) inductively coupled plasmas(ICP) have the promise to address some of the above challenges. Typical commercial ICP reactors consists of 2 RF power supplies, the RF source which is fed to the antenna coils of the ICP source and RF bias applied to the substrate. Accordingly, 3 main different regimes of operation for pulsed plasmas might take place. The first, known as source pulsing, in which the source is operating in PRF mode while having the bias in continuous wave(CW) mode. The second is bias pulsing i.e. source in CW mode while the bias is in PRF mode. The third one is synchronized pulsing, for which both source and bias are pulsed simultaneously at the same frequency and duty cycle.

Recently we have evaluated the impact of synchronized pulsing plasma on gate etch for sub-50nm DRAM applications. The evaluation included basic etching characteristics such as average etch rate, uniformity and selectivity, 35nm gate critical dimension(CD) uniformity and profile control, and plasma induced damage. It was demonstrated that by control of the synchronous pulse parameters extends the plasma operating conditions range aiming to improve processes for finer features. In particular, we have shown gate CD controllability, PID mitigation, and significant reduction in electron shading effect and in the gate leakage current along with improving the electrical performance of the overall device. 2D plasma and feature scale modeling results will be used to illustrate the basic physics of synchronous pulsing, in particular its effect on the ion energy distribution.