AVS 53rd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuP

Paper PS2-TuP13
A Comprehensive Characterization of the Silicon Substrate Surfaces Damaged by Plasma Processes and the Impacts on Future Scaled Devices

Tuesday, November 14, 2006, 6:00 pm, Room 3rd Floor Lobby

Session: Etching and Process Integration Poster Session
Presenter: K. Eriguchi, Kyoto University, Japan
Authors: K. Eriguchi, Kyoto University, Japan
K. Nakamura, Kyoto University, Japan
M. Kamei, Kyoto University, Japan
D. Hamada, Kyoto University, Japan
H. Fukumoto, Kyoto University, Japan
K. Ono, Kyoto University, Japan
Correspondent: Click to Email
The surfaces of silicon substrates after the plasma exposure have been investigated by primarily using optical techniques; photoreflectance (PR) spectroscopy and spectroscopic ellipsometry. Electron Cyclotron Resonance (ECR) and DC plasma sources with Ar-based gas mixtures were employed to induce the defect generation in the substrates for various biasing conditions, i.e., ion bombardment energies, and process durations. The PR studies with an s-polarized probe beam at the 80° grazing-incidence angle have revealed the decrease in the reflectance change by the plasma exposure, but no significant shift of the optical transition energy at around 3.3-3.4 eV, indicating that the carrier recombination centers are generated in the vicinity of the interface between the natural oxide layer and silicon substrate. The ellipsometric analysis based on the classical dispersion has identified the damaged-layer and determined the thickness as thinner than 6 nm for all the process conditions conducted in this study. The substrate resistivity measurement has shown the increase in the standard deviation of the values by the plasma exposure. The defects in the substrate surface region were further identified distinctly by the present PR setup for the sample treated by the ECR plasma system under no biasing condition (Ar/O@sub 2@ gas mixture). Based on this new finding, we conclude that the thickness and electrical property of the plasma-damaged layer should be taken into account for future scaled devices, e.g., those with the junction depth shallower than 10 nm.