Paper PS2-TuP12
Empiric Study on the Effects of Two Different Film Stack Approaches on Gate Etching in Typical High-Density Plasma for Advanced Embedded Logic & Flash Systems
Tuesday, November 14, 2006, 6:00 pm, Room 3rd Floor Lobby
Advanced Embedded logic & flash memory systems (120nm and below) requires necessarily new and complex solutions in terms of process integration. An empiric study on the effects of two different film stack approaches on gate etching in typical high-density plasmas will be discussed in this paper. Profile evolution of a high aspect ratio dense pattern could change in significant way if between photoresist (193nm) and polysilicon a thin oxide layer has (or not) been grown by a previous oxidation. In the top-poly oxidation approach, for the first time, evident notching at the middle height of the structure (not at the bottom as typically known) has been seen; the observed phenomenon depends on the pattern density and the electrical connection status of the polysilicon lines. An extensive morphological analysis has been performed and the results suggest the presence of three correlated effects during the etching: a) electron shading; b) resist bending (depending on the local charging of the neighboring surfaces); c) notching mechanism.@footnote 1@ Dependence on the aspect ratio (different resist thickness) and on the film stack (w/wo top oxidation) has been empirically characterized. A Process window on the different etching steps has permitted to identify the strategy to reduce substantially the morphological issues, e.g. towards a straight gate profile. Achieved results are consistent with the electron shading effect, notching theory and with the relationship between the resist thermo-physical properties (T@sub g@) and its thickness.@footnote 2@ @FootnoteText@ @footnote 1@ R.J. Dhul, S.J. Pearton (Eds.), Handbbok of Advanced Plasma Processing Techniques, Springer Ed., 257-308 (2000)@footnote 2@ N. Vourdas, A.G. Boudouvis, E. Gogolides, Microelectronic Engineering 78-79, 474 (2005)