AVS 53rd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuP

Paper PS2-TuP10
Silicon Surface Treatment of Contact Hole in Memory Device by Downstream Plasma

Tuesday, November 14, 2006, 6:00 pm, Room 3rd Floor Lobby

Session: Etching and Process Integration Poster Session
Presenter: C.W. Kim, PSK-inc, Korea
Authors: C.W. Kim, PSK-inc, Korea
C.W. Lee, PSK-inc, Korea
H.B. Seo, PSK-inc, Korea
K.T. Kim, PSK-inc, Korea
J.K. Yang, PSK-inc, Korea
Correspondent: Click to Email
Silicon surface of contact hole has been treated by fluorine based plasma using downstream type ICP source. Silicon etch rate and uniformity had been investigated on 12 inch blanket wafer as a function of process parameters. The profile of etch rate map is changed from center high to edge high etch rate tendency by controlling total gas flow rate and this make it possible to control etch uniformity. The etch selectivity of silicon to silicon nitride, as SAC barrier material, is studied with the various gas mixture ratio of feed stock gas. Commonly higher etch selectivity is obtained under the high silicon etch rate condition due to the difference of etch characteristics between silicon and silicon nitride film but higher selectivity more than 7:1, silicon to nitride, can be achieved over wide range of silicon etch rate by adjusting gas mixture ratio. Finally, the etch uniformity and etch profile of bit line contact and storage node contact hole is examined by TEM on 12 inch whole pattern wafer.