AVS 53rd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuA

Paper PS2-TuA7
Three-Dimensional Control of Interconnect Features: Sidewall Roughness Transfer During Patterning Processes

Tuesday, November 14, 2006, 4:00 pm, Room 2011

Session: Etch for Advanced Interconnect II
Presenter: T. David, CEA-LETI-France
Authors: T. David, CEA-LETI-France
J. Foucher, CEA-LETI-France
N. Posseme, CEA-LETI-France
A. Jacquier, CEA-LETI-France
A.-L. Fabre, CEA-LETI-France
Correspondent: Click to Email
Dimensional control is a key challenge for present and future interconnect technology generations. The dominant architecture, damascene, requires tight control of patterning. To extract maximum performance, interconnect structures cannot tolerate variability in profiles without producing undesirable RC degradation. For advanced nodes, feature size effects, such as electron surface scattering, will increase the effective resistivity and may require new technological development. Indeed characterization shows significant contributions to resistivity by scattering from both grain boundaries and sidewall patterns. In this work, we investigate the sidewall roughness (LWR, LER) transfer during interconnect patterning. The roughness is first calculated by performing threshold analysis of top down SEM images. However this technique does not take into account variations along feature height. Therefore, we have used a new 3D CD-AFM (Dimension X-3D) which enables us to characterize roughness along the features after each technological step of C065 etching processes on 300mm wafers. Trenches with various dimensions are patterned with conventional ArF photoresist. Then, the patterns are transferred into a metallic hard mask before etching of capping and dielectric layers. First results show a decrease of LWR during lithography pattern transfer into the metallic hard mask. Moreover LWR stays constant along profile height during capping and dielectric etching. Regarding LER, it seems that a slight increase is observed when going from the dense dielectric material (capping layer) to the more porous one (dielectric layer) while keeping LWR constant.