To reduce the cross-talk and power consumption among the on-chip interconnects, low-dielectric constant (low-k) films have been introduced. However, there are several problems on etching/ ashing process, such as the low etching selectivity to the mask, and the ashing damage of low-k film. In this paper, we will show 2 types of highly-selective and low-damage processes, (I) multi-hard-mask process and (II) advanced neutral beam process. We developed the 4 layered multi-hard-mask process without ashing damage. By controlling the radical ratio of carbon to oxygen, the etching selectivity to SiO@sub 2@ hard mask is kept high. The parasitic capacitance of Cu/ porous SiOCH in this process reduced about 7 % as compared with that in conventional via first DD process because of ashing-free process. The hard mask process is effective to reduce the damage, however, it is difficult to control the etching uniformity and hard-mask shouldering for various damascene structure. As an advanced process, we developed a newly advanced neutral beam system. The etching selectivity was drastically improved, and ashing damages were reduced significantly. We speculated that this is due to the elimination of exposure of ultraviolet light. Accordingly, the neutral beam system is a promising candidate for use in porous low-k damascene processes beyond 45nm node ULSIs.