AVS 53rd International Symposium
    Plasma Science and Technology Thursday Sessions
       Session PS1-ThA

Paper PS1-ThA9
Improvement of Programming Characteristics of Ge2Sb2Te5 Thin Films by Incorporating SiO2 for Application of PcRAM

Thursday, November 16, 2006, 4:40 pm, Room 2009

Session: Plasma Processing for High-K/III-V’s and Smart Materials
Presenter: J.H. Oh, Seoul National University, Korea
Authors: S.W. Ryu, Seoul National University, Korea
J.H. Oh, Seoul National University, Korea
B.J. Choi, Seoul National University, Korea
S.K. Hong, Hynix Semiconductor Inc., Korea
C.S. Hwang, Seoul National University, Korea
H.J. Kim, Seoul National University, Korea
Correspondent: Click to Email
In an effort to overcome the scaling limit of the floating gate non-volatile memory (NVM) technology below the 30nm design rule, the semiconductor industry has been forced to find alternative NVM.@footnote 1-4@ Phase change random access memory (PCRAM) attracts great interest not only because it satisfies the various demands for NVM devices but also because its fabrication process is relatively simple. However, the high level of reset current has been the major obstacle for further scaling of PCRAM because of the limited on-current drive capability of the cell transistor (<1mA/µm) and then unexpected crystallization of unstable amorphous state has resulted from low crystallization temperature of Ge @sub 2@Sb@sub 2@Te@sub 5@ (GST). The phase change characteristics of GST films for phase change random access memory devices were improved by incorporating SiO@sub 2@ into the GST film through co-sputtering at room temperature. Isochronal annealing showed an increased resistivity of the crystallized GST films in proportion to the incorporated quantity of SiO@sub 2@ which leads to a reduction in the writing current. Incorporated SiO@sub 2@ also inhibits crystallization of the amorphous GST film which can improve the long term stability of the meta-stable amorphous phase. @FootnoteText@ @footnote 1@S. Hudgens and B. Johnson, Mater. Res. Soc. Bull. November, 2002, p.829. @footnote 2@S. Lai, Tech. Dig. Int. Electron. Devices Meet. Washington, DC, 2003, p.255. @footnote 3@S.Y. Lee and K. Kim, Int. Conference on Integrated Circuit Design and Technology, 2004, p.45. @footnote 4@Y. N. Hwang, S. H. Lee, S.J. Ahn, S.Y. Lee, K.C. Ryoo, H.S. Hong, H.C. Koo, F. Yeung, J.H. Oh, H.J. Kim, W.C. Jeong, J.H. Park, H. Horri, Y.H. Ha, J.H. Yi, G.H. Koh, G.T. Jeong, H.S. Jeong and K. KiM, Tech. Dig. Int. Electron. Devices Meet. Washington, DC, 2003, p.893 .