AVS 53rd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS1+MS+NM-TuM

Paper PS1+MS+NM-TuM5
Plasma Etching of Nano-Scale, Sub-10nm, Features

Tuesday, November 14, 2006, 9:20 am, Room 2009

Session: Plasma Patterning
Presenter: Y. Zhang, IBM Research
Authors: Y. Zhang, IBM Research
C.T. Black, IBM Research
H.-C. Kim, IBM Research
E.M. Sikorski, IBM Research
T. Dalton, IBM Research
Correspondent: Click to Email
Features Patterning nano-scale semiconductor features with precision imposes many new challenges for plasma etching. One of the challenges is that as the sizes of nano-scale features shrinking down to the sub-10nm regime, Plasma etching seems to approach to the limits. In this paper, we report the recent results of studying plasma etching of true nano-scale features using tow kinds of nano-sacle patterns. The first type of samples is diblock copolymer (similar to resist) self assembled nano holes and lines. The second kind samples are self-assembled organosilicate (similar to silicon oxide) nano patterns. With samples pattern, arrays of nano holes or nano lines' dimensions in the range of ~10nm, we studied plasma etching challenges for transferring nano-scale patterns into different materials (silicon, and silicon dioxide) in different plasma chemistries and process conditions. By varying the thickness of masks, the characteristics of aspect ratio dependence vs. "real" etching limits due to the sizes of sub-10nm nano-scale features were studied. The impacts of mask selectivity and line edge roughness (LER) to transferring sub-10nm patterns will be also discussed.