AVS 53rd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS1+MS+NM-TuM

Paper PS1+MS+NM-TuM1
Resolving Gate Patterning Issues at sub 65 nm Technology Nodes

Tuesday, November 14, 2006, 8:00 am, Room 2009

Session: Plasma Patterning
Presenter: T.J. Kropewnicki, Freescale Semiconductor, Inc.
Authors: T.J. Kropewnicki, Freescale Semiconductor, Inc.
C.-C. Fu, Freescale Semiconductor, Inc.
Correspondent: Click to Email
According to the 2005 edition of the International Technology Roadmap for Semiconductors, the physical gate length of high performance transistors at the 65 nm technology node is expected to be 25 nm in 2007, decreasing to 18 nm at the 45 nm node in 2010. Clearly, these goals present a clear challenge to photolithography and etch, which together are responsible for resolving these features on wafers. In addition to the pure scaling aspects of technology progression are the many additional enhancements such as stressors, which are being used to push the performance of silicon circuits. In certain integration schemes, these stressors add complexity to the transistor gate stack and accelerate photoresist bending and line collapse which cause etch masking, and ultimately variable, uncontrollable line widths. This paper will begin with a brief description of the transistor module process flow, highlighting the new challenges introduced to the gate stack etch at sub 65nm technology nodes. Next, a combination of enhancements in the gate photolithography and etch steps used to address these challenges will be presented. Results from these experiments will show a 50% reduction in across wafer line width variation, and a near 100% reduction in the incidence of polysilicon pattern distortion. Finally, the possible mechanisms for the increased levels of polysilicon pattern distortion seen with advanced transistor modules will be discussed.