AVS 53rd International Symposium
    Manufacturing Science and Technology Tuesday Sessions
       Session MS-TuA

Paper MS-TuA4
Virtual Integrated Processing for IC Manufacturing

Tuesday, November 14, 2006, 3:00 pm, Room 2018

Session: Process Integration and Modeling for Nano-scale Semiconductor Devices
Presenter: H. Simka, Intel Corporation
Authors: R. Chalupa, Intel Corporation
D.G. Thakurta, Intel Corporation
L. Jiang, Intel Corporation
H. Simka, Intel Corporation
S. Shankar, Intel Corporation
Correspondent: Click to Email
As each new semi-conductor technology becomes more complex, targeted simulations can lead to significant savings in process development time and cost. These are achieved by providing insights into process behavior and quantifying effects of process knobs on performance. Due to the complexity of physical phenomena involved, each process simulator may itself consist of multiple (possibly linked) modules each aimed at different length and/or time scales or different operating regimes. In Electroplating (EP) process for backend (BE) interconnect formation for example, wafer-scale events are often governed by electrostatic potential fields where current distributions are estimated based on local conductivities. Feature scale (less than 1-100 microns) events are often governed by transport-reaction events in shape-changing domains. Availability of accurate simulation tools allows investigations of dependence of a BE step to those preceding it, and its effects on subsequent steps. This "virtual processing" provides information useful in investigation of process input requirements, performance limits, scaling, and other integration issues. One example of process interaction modeling is in EP and CMP areas where models were used to explore film planarity for various realistic chip layouts. Our integrated BE simulator provides an effective way to explore solutions not readily accessible in experiments due to cost and time constraints. These model components have played key roles in developing advanced BE modules, including alternative deposition and planarization processes for 90 nm technology.