AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoA

Paper PS2-MoA5
Silicon Gate Etching using Amorphous Carbon Hard Mask

Monday, October 31, 2005, 3:20 pm, Room 304

Session: Silicon Etching
Presenter: F. Lazzarino, CNRS/LTM, France
Authors: F. Lazzarino, CNRS/LTM, France
P. Gouraud, STMicroelectronics, France
T. Chevolleau, CNRS/LTM, France
B. Pelissier, CNRS/LTM, France
G. Cunge, CNRS/LTM, France
L. Vallier, CNRS/LTM, France
O. Joubert, CNRS/LTM, France
T. Lill, Applied Materials
Correspondent: Click to Email
Nowadays, the development of new integrated circuit generations requires the introduction of new materials. Among them, the amorphous carbon (a-C) is a promising candidate as a hard mask for gate etching processes due to its high selectivity to silicon (6:1). Moreover, since the conventional photolithography is not able to achieve resist linewidth lower than 80 nm, the trimming of a-C can be used as a new strategy to obtain sub-30 nm gate length. In this paper, an etch integration scheme using a-C hard mask is evaluated on 300 mm wafers and fully characterized for undoped, n-doped and p-doped wafers. The gate stack is composed of 1.2 nm SiON gate oxide, 100 nm polysilicon film, 100 nm PECVD amorphous carbon, 20 nm dielectric anti-reflective coating (DARC). The wafers are patterned with a 193 nm lithography and etched in an industrial inductively coupled plasma reactor. The resist trimming combined with the a-C trimming is investigated using different types of halogen chemistries containing oxygen (HBr/O@sub 2@, Cl@sub 2@/O@sub 2@,...) which allow to obtain sub-30 nm gate structures. The polysilicon gate is etched in conventional HBr/Cl@sub 2@/O@sub 2@ chemistries and the impact of the plasma parameters on the etch rates and both undoped and doped (n and p) gate profile is evaluated. Futhermore, chemical topography analyses by quasi in-situ X-ray Photoelectron Spectroscopy (XPS) are performed in order to correlate the etch profiles with the chemical composition of the passivation layers deposited on the sidewalls of the polysilicon gate.