AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoA

Invited Paper PS2-MoA3
Silicon Etching Beyond the 90nm Technology Node: the Need for Total Parameter Flexibility

Monday, October 31, 2005, 2:40 pm, Room 304

Session: Silicon Etching
Presenter: A.M. Paterson, Applied Materials
Authors: A.M. Paterson, Applied Materials
T. Panagopoulos, Applied Materials
T.J. Kropewnicki, Applied Materials
V. Todorow, Applied Materials
A. Matyushkin, Applied Materials
B. Hatcher, Applied Materials
S. Pamarthy, Applied Materials
N. Gani, Applied Materials
A. Khan, Applied Materials
S. Deshmukh, Applied Materials
M. Shen, Applied Materials
T. Lill, Applied Materials
J.P. Holland, Applied Materials
Correspondent: Click to Email
As CMOS technology node sizes push further into the nano-scale domain (sub 100nm) it has initiated new challenges for the silicon etching of logic and DRAM structures. In order to keep abreast of Moore's Law, new gate materials, geometries and architectures are currently being explored by IC manufactures with the intent of driving the node size to 32 nm by the end of this decade. Such device scaling brings new demands to wafer etch suppliers, with even more stringent etch requirements expected. At present, 90 nm technology is the smallest node in volume production, with the gate lengths being approximately 65 nm and CD bias requirements of 4 nm 3s over the entire 300 mm wafer, 3 mm edge exclusion. CD bias control is of paramount importance as it directly correlates to processor speed and cost. For smaller nodes the combination of resist trimming and curing (to prevent Line Edge Roughness (LER)) and process parameter flexibility become even more crucial in controlling the gate CD bias. This presentation will focus on the research and development work undertaken at Applied Materials to produce novel silicon etch equipment that will enable IC manufactures to obtain their goals for continued node size reduction. Experimental and theoretical work will be discussed showing the many novel features of an advanced 300 mm Applied Centura® DPS® process chamber for sub-65 nm gate, Shallow Trench Isolation (STI) and capacitor etches. This chamber has been designed to produce precise resist trimming / curing with total process step parameter flexibility allowing CD bias control of less than 3 nm 3s, 2 mm edge exclusion, for sub-65 nm technologies.